Who invented x86 virtualization

Send somebody a link to this page. Your Name. Friend's Name. Recipient's Email. Enter security code:. Request More Information. Contact centre. Contact Centre. Customer IT Support There's little reason [for IBM] to invest in trying to make money by building a better [x86] hypervisor.

Where the real opportunity exists in adding value for data centers is much higher up the stack. IBM and VMware have advanced similar concepts that leverage virtualization technologies to aggregate data center resources into small numbers of logical computing pools that can be managed from single consoles. Rymarczyk is working with IBM's Tivoli software team to develop architectures that will lead to more dynamic and responsive data centers. It's largely management software that is going to make the difference.

Here are the latest Insider stories. More Insider Sign Out. Sign In Register. Sign Out Sign In Register. Latest Insider. Check out the latest Insider stories here. More from the IDG Network. IBM ups the ante with Power virtualization. How Virtualization Improves Software Development. Join the Network World communities on Facebook and LinkedIn to comment on topics that are top of mind. In addition to the monitor 47 , personal computers typically include other peripheral output devices not shown , such as speakers and printers.

The exemplary system of FIG. The personal computer 20 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer The remote computer 49 may be another personal computer, a server, a router, a network PC, a peer device or other common network node, and typically includes many or all of the elements described above relative to the personal computer 20 , although only a memory storage device 50 has been illustrated in FIG.

The logical connections depicted in FIG. Such networking environments are commonplace in offices, enterprise wide computer networks, intranets and the Internet. When used in a LAN networking environment, the personal computer 20 is connected to the LAN 51 through a network interface or adapter When used in a WAN networking environment, the personal computer 20 typically includes a modern 54 or other means for establishing communications over the wide area network 52 , such as the Internet.

The modem 54 , which may be internal or external, is connected to the system bus 23 via the serial port interface In a networked environment, program modules depicted relative to the personal computer 20 , or portions thereof, may be stored in the remote memory storage device. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

While it is envisioned that numerous embodiments of the present invention are particularly well-suited for computerized systems, nothing in this document is intended to limit the invention to such embodiments. In general, registers are small data holding places that are a typical part of a computer processor. A register may hold a computer instruction, a storage address, or any kind of data such as a bit sequence or individual characters , and some instructions specify registers as part of the instruction.

For example, an instruction may specify that the contents of two defined registers be added together and then placed in a specified register overwriting whatever contents were previously stored in this destination register. In most cases, a register must be large enough to hold an instruction—for example, in a bit instruction computer, a register must be at least thirty-two 32 bits in length. In some computer designs, there are smaller registers—for example, half-registers and even quarter-registers—for shorter instructions or other purposes.

Depending on the processor design and language rules, registers may be numbered or have arbitrary names. The x86 IA32 architecture has a specific set of registers comprising the general registers, the segment registers, the EFLAG register, the control registers, and a variety of others registers. As illustrated in FIG. The system registers not shown comprises a plurality of control registers that are discussed later herein.

Above each VM and are guest operating systems A and B respectively. Emulation program emulates a guest hardware architecture and a guest operating system Software application in turn runs on guest operating system In the emulated operating environment of FIG.

There are two primary methods for processor virtualization: emulation and direct execution. A hybrid of these two approaches is also possible. Emulation involves the use of an interpreter or binary translation mechanism and is the only feasible choice when implementing a.

VM on a system where the guest and host processors differ significantly. Emulation is also needed in some situations where the guest and host processors are the same but the processor provides inadequate virtualization support.

Certain operating modes of the x86 architecture fall into this category. While emulation is the most flexible and compatible virtualization mechanism, it is usually not the fastest. Both interpretation and binary translation impose a runtime overhead.

A binary translation mechanism is more complex than an interpreter, but it can mitigate some of the performance loss. Direct execution is generally faster than emulation. A good direct-execution implementation comes within a few percentage points of native performance.

In this regard, direct execution relies on the fact that most modern processors differentiate between user level and privileged level software. Software running in privileged mode is able to access all processor resources including registers, modes, settings, in-memory data structures, etc. User level mode, in contrast, is intended for untrusted software that performs the majority of the computational work in a modern system. To this end, most processors make a strict distinction between user-level state and privileged-level state, where access to privileged-level state is typically not allowed when the processor is operating at user level, which in turn allows trusted software typically the operating system to protect key resources and prevent a buggy or malicious piece of user-level software from crashing the entire system.

Direct execution of user-level code in a virtual machine is typically straight-forward and requires no special tricks because, when running virtualized user-level code, any privilege violations that occur on the hardware are simply passed along to the virtual machine, simulating the behavior of a non-virtualized processor running at user level.

However, direct execution of privileged-level code is trickier because, for the virtual machine, this typically involves running privileged-level code in the VM at user level on the physical hardware.

When a sensitive instruction is executed by the processor running at user level, the processor typically generates a privilege violation trap because code executing at the user-level is not permitted to execute sensitive instructions. This violation trap, in turn, invokes an underlying trap handler resident in the virtual machine monitor or VMM which, in effect, forms the virtual hardware aspect of the virtual machine. The VMM's trap handler for handling violation traps from the physical hardware is responsible for intercepting the violation trap and, in regard to the VM, for emulating the expected effects or results of the privileged instruction, and then for returning control back to the subsequent instruction to be executed in the VM.

Emulation of a privileged instruction in this way often involves the use of shadow state that is private to a particular VM instance. In this event, the VMM's trap handler would determine the cause of the trap and refer to a PMR shadow value that is private to the instance of the associated VM. However, depending on the frequency of trapping instructions and the cost of handling a trap, this technique may impose a significant performance penalty.

An idealized processor intended for virtualization is said to be strictly virtualizable. Unfortunately, IA32 and IA64 do not. Simply put, a strictly virtualizable processor allows for the implementation of a direct execution virtualization mechanism that meets the following requirements:.

Goldberg, who did significant early research in the field of virtual machines, formally defined several requirements for a processor to support virtualization. In less formal and more modern terms, a strictly virtualizable processor must exhibit the following properties. Incorporates an MMU or similar address translation mechanism.

Divides all processor state into either privileged state or user state; privileged state should include any control or status fields that indicates the current privilege level. Causes a trap when any access to privileged state whether read or write is attempted at user level. Optionally causes a trap when user-level code attempts to access non-privileged state that should be virtualized e. All in-memory processor structures are either stored outside of the current address space or are protectable from errant or malicious memory accesses within the VM.

Any processor state at the time of an interrupt or trap can be restored to its pre-trap state after the interrupt or trap is handled.

In addition, a strictly virtualizable processor also supports the curious ability to virtualize recursively—i. Of course, while these required properties are necessary for correct processor virtualization, they do not guarantee efficient virtualization.

Modern x86 processors contain a mode called virtual or v86 for short. This mode allows well-behaved real-mode code to run within a protected-mode virtual machine. A set of virtualization assists were added starting with the to reduce the virtualization overhead of code running within v86 mode.

These virtual mode extensions or VME for short provide three specific virtualization assists:. Virtual mode and VME are useful for running legacy application-level software within a protected-mode operating system environment.

However, v86 mode is not flexible enough to run all real-mode code. At the same time VME was incorporated into the IA32 architecture, a companion facility was introduced for use with protected-mode code. This facility is referred to as protected-mode virtual interrupts or PVI for short. Furthermore, while the processor correctly handles certain instructions that modify the IF, it does not handle others.

For these reasons, PVI has proven to be an ill-conceived and poorly architected virtualization assist which, in practice, is essentially useless. At the time you write your program, your Java code is not compiled.

Instead, it is converted into Java Byte Code, until just before the program is executed. Since the JRE compiles the software just before running, the developer does not need to worry about what operating system or hardware platform the end user will run the application on; and the user does not need to know how to compile a program, that is handled by the JRE..

Whenever a java application is run, it is run inside of the Java Virtual Machine. You can think of the Java Virtual Machine is a very small operating system, created with the sole purpose of running your Java application. You can write the application once, and run anywhere. At least that is the idea; there are some limitations.

With increased complexity came expanding administrative costs driven by the need to hire more experienced IT professionals, and the need to carry out a wide variety of tasks, including Windows Server backup and recovery.

These actions required more manual intervention in processes than many IT budgets could support. Server maintenance costs, especially those tied to Windows Server backup, were climbing and more personnel were required to work through an increasing number of day-to-day tasks.

Just as important were the issues of how to limit the impact of server outages, improve business continuity and create more robust disaster recovery plans. Still, it served as a powerful inspiration for VMware to reviving the concept and apply it to x86 machines.